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JANSR2N7292
Formerly FRF150R4
June 1998
25A, 100V, 0.070 Ohm, Rad Hard, N-Channel Power MOSFET
Description
The Intersil Corporation has designed a series of SECOND GENERATION hardened power MOSFETs of both N-Channel and P-Channel enhancement types with ratings from 100V to 500V, 1A to 60A, and on resistance as low as 25m. Total dose hardness is offered at 100K RAD (Si) and 1000K RAD (Si) with neutron hardness ranging from 1E13 for 500V product to 1E14 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current limiting and 2E12 with current limiting. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and neutron (no) exposures. Design and processing efforts are also directed to enhance survival to dose rate (GAMMA DOT) exposure. Also available at other radiation and screening levels. See us on the web, Intersil's home page: http://www.semi.harris.com. Contact your local Intersil Sales Office for additional information.
Features
* 25A, 100V, rDS(ON) = 0.070 * Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM * Photo Current - 7.0nA Per-RAD(Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2
Ordering Information
PART NUMBER JANSR2N7292 PACKAGE TO-254AA BRAND JANSR2N7292
Symbol
D
Die family TA17651. MIL-PRF-19500/605.
G
S
Package
TO-254AA
G S D
CAUTION: Beryllia Warning per MIL-S-19500 refer to package specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4293.2
2-18
JANSR2N7292
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified JANSR2N7292 100 100 25 20 75 20 125 50 1.00 75 25 75 -55 to 150 300 9.3 UNITS V V A A A V W W W/oC A A A oC oC g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJC, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC MIN 100 2.0 1.0 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 50V, ID = 25A TYP MAX 5.0 4.0 25 250 100 200 1.84 0.070 0.140 134 628 642 490 552 314 17 46 164 1.0 48 UNITS V V V V A A nA nA V ns ns ns ns nC nC nC nC nC
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage
Zero Gate Voltage Drain Current
IDSS IGSS VDS(ON) rDS(ON) td(ON) tr td(OFF) tf Qg(TOT) Qg(10) Qg(TH) Qgs Qgd RJC RJA
VDS = 80V, VGS = 0V VGS = 20V VGS = 10V, ID = 25A ID = 20A, VGS = 10V
Gate to Source Leakage Current
Drain to Source On-State Voltage Drain to Source On Resistance
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Not on slash sheet) Gate Charge at 10V Threshold Gate Charge (Not on slash sheet) Gate Charge Source Gate Charge Drain Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
VDD = 50V, ID = 25A, RL = 2.0, VGS = 10V, RGS = 25
Source to Drain Diode Specifications
PARAMETER Forward Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 25A ISD = 25A, dISD/dt = 100A/s MIN 0.6 TYP MAX 1.8 1400 UNITS V ns
2-19
JANSR2N7292
Electrical Specifications up to 100K RAD
PARAMETER Drain to Source Breakdown Volts Gate to Source Threshold Volts Gate to Body Leakage Zero Gate Leakage Drain to Source On-State Volts Drain to Source On Resistance NOTES: 1. Pulse test, 300s Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 10V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . (Note 3) (Note 3) (Notes 2, 3) (Note 3) (Notes 1, 3) (Notes 1, 3) TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON) TEST CONDITIONS VGS = 0, ID = 1mA VGS = VDS, ID = 1mA VGS = 20V, VDS = 0V VGS = 0, VDS = 80V VGS = 10V, ID = 25A VGS = 10V, ID = 20A MIN 100 2.0 MAX 4.0 100 25 1.84 0.070 UNITS V V nA A V
Typical Performance Curves
40
Unless Otherwise Specified
100 30 ID , DRAIN (A) ID , DRAIN CURRENT (A)
TC = 25oC 100ms 1ms 10ms
10
20
10
1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
100ms
0 -50
0
50
100
150
0.1
100
TC , CASE TEMPERATURE (oC)
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
10
THERMAL RESPONSE (ZJC)
1 0.5 0.2 0.1 0.05 0.02 0.01
NORMALIZED
0.1
PDM SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC t1 t2
0.01
0.001 10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-20
JANSR2N7292 Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L + CURRENT I TRANSFORMER AS BVDSS tP IAS 50 + VDD VDS VDD
-
VARY tP TO OBTAIN REQUIRED PEAK IAS VGS 20V
DUT 50V-150V 50 tAV
0V
tP
FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 5. UNCLAMPED ENERGY WAVEFORMS
VDD
tON td(ON)
tOFF td(OFF) tr tf 90%
RL VDS VGS = 10V DUT 0V RGS
VDS
90%
10%
10%
90% VGS 10% 50% PULSE WIDTH 50%
FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 7. RESISTIVE SWITCHING WAVEFORMS
10V
QG
QGS VG
QGD
CHARGE
FIGURE 8. BASIC GATE CHARGE WAVEFORM
2-21
JANSR2N7292 Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified
PARAMETER Gate to Source Leakage Current Zero Gate Voltage Drain Current Drain to Source On Resistance Gate Threshold Voltage NOTES: 4. Or 100% of Initial Reading (whichever is greater). 5. Of Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS VGS = 20V VDS = 80% Rated Value TC = 25oC at Rated ID ID = 1.0mA MAX 20 (Note 4) 25 (Note 4) 20% (Note 5) 20% (Note 5) UNITS nA A V
Screening Information
TEST Gate Stress Pind Pre Burn-In Tests (Note 6) Steady State Gate Bias (Gate Stress) VGS = 30V, t = 250s Required MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours All Delta Parameters Listed in the Delta Tests and Limits Table MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours 5% MIL-S-19500, Group A, Subgroups 2 and 3 JANS
Interim Electrical Tests (Note 6) Steady State Reverse Bias (Drain Stress)
PDA Final Electrical Tests (Note 6)
NOTE: 6. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL SOA IAS VSD VSD TEST CONDITIONS VDS = 80V, t = 10ms VGS(PEAK) = 15V, L = 0.1mH tH = 100ms; VH = 25V; IH = 4A tH = 500ms; VH = 25V; IH = 4A MAX 5 75 136 187 UNITS A A mV mV
2-22
JANSR2N7292 Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning Attributes Data Sheet Hi-Rel Lot Traveler HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A G. Group B H. Group C I. Group D - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet - Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data
G. Group B
H. Group C
I. Group D
2-23
JANSR2N7292 TO-254AA
3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE
A E OP A1
INCHES SYMBOL A MIN 0.249 0.040 0.035 0.790 0.535 MAX 0.260 0.050 0.045 0.800 0.545
MILLIMETERS MIN 6.33 1.02 0.89 20.07 13.59 MAX 6.60 1.27 1.14 20.32 13.84 NOTES 2, 3 4 4 4 -
Q H1
A1 Ob D
D
E e e1 H1 J1
0.065 R MAX. TYP.
0.150 TYP 0.300 BSC 0.245 0.140 0.520 0.139 0.110 0.265 0.160 0.560 0.149 0.130
3.81 TYP 7.62 BSC 6.23 3.56 13.21 3.54 2.80 6.73 4.06 14.22 3.78 3.30
L OP Q
L
Ob
1
2
3 J1
e e1
NOTES: 1. These dimensions are within allowable dimensions of Rev. A of JEDEC outline TO-254AA dated 11-86. 2. Add typically 0.002 inches (0.05mm) for solder coating. 3. Lead dimension (without solder). 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Die to base BeO isolated, terminals to case ceramic isolated. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its' compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
2-24

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